A 0.52V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung*, Wei-Siang Su and Chi-Kuang Lo |
2016 |
Partial parity cache and data cache management method to improve the performance of an SSD-based RAID |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung* and Hao-Hsiang Hsu |
2014 |
High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung*, Duo Sheng, and Sung-En Shen |
2014 |
A wide-range low-cost all-digital duty-cycle corrector |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung*, Duo Sheng, and Chang-Jun Li(學生), “,” , vol. 23, no. 11, pp. , Nov. 2015 |
2014 |
A low-cost low-power all-digital spread-spectrum clock generator, |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung*, Duo Sheng, and Wei-Da Ho |
2014 |
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications |
IEICE Electronics Express (ELEX) |
Duo Sheng*, Ching-Che Chung, Hsiu-Fan Lai and Shu-Syun Jhao |
2013 |
A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS |
IEICE Electronics Express (ELEX) |
Ching-Che Chung*, Duo Sheng, and Wei-Da Ho |
2013 |
A high-performance wear-leveling algorithm for flash memory system |
IEICE Electronics Express (ELEX) |
Ching-Che Chung*, Duo Sheng, and Ning-Mi Hsueh |
2012 |
An ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity |
Electronics Letters |
Wei-Hao Sung, Ming-Che Lee, Ching-Che Chung, and Chen-Yi Lee* |
2012 |
A low-power DCO using interlaced hysteresis delay cells |
IEEE Transactions on Circuits and Systems II: Express Briefs |
Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, and Chen-Yi Lee* |
2012 |
An all-digital large-N audio frequency synthesizer for HDMI applications |
IEEE Transactions on Circuits and Systems II: Express Briefs |
Ching-Che Chung*, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, and Fang-Nien Lu |
2012 |
Monotonic and low-power digitally controlled oscillator with portability for SoC applications |
Electronics Letters |
Duo Sheng*, Ching-Che Chung, Jhih-Ci Lan, and Hsiou-Fan Lai |
2012 |
A low-power and portable spread spectrum clock generator for SoC applications |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Duo Sheng, Ching-Che Chung, and Chen-Yi Lee |
2011 |
A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology |
IEEE Journal of Solid-State Circuits |
Ching-Che Chung* and Chiun-Yao Ko |
2011 |
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65 nm CMOS technology |
IEICE Electronics Express (ELEX) |
Ching-Che Chung*, Duo Sheng, and Sung-En Shen |
2011 |
A 600 kHz to 1.2 GHz all-digital delay-locked loop in 65 nm CMOS technology |
IEICE Electronics Express (ELEX) |
Ching-Che Chung*, Duo Sheng, and Chia-Lin Chang |
2011 |
Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology |
IEEE Transactions on Circuits and Systems II: Express Briefs |
Ching-Che Chung*, Chiun-Yao Ko, and Sung-En Shen |
2011 |
An autocalibrated all-digital temperature sensor for on-chip thermal monitoring |
IEEE Transactions on Circuits and Systems II: Express Briefs |
Ching-Che Chung* and Cheng-Ruei Yang |
2011 |
Wide duty cycle range synchronous mirror delay designs |
Electronics Letters |
Duo Sheng, Ching-Che Chung, and Chen-Yi Lee |
2010 |
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications |
IEICE Electronics Express (ELEX) |
Duo Sheng, Ching-Che Chung, and Chen-Yi Lee |
2010 |