林 泰吉（国立中正大学资讯工程学系）
职称 副教授兼芯片系统研究中心主任
姓名 林 泰吉（国立中正大学资讯工程学系）
联络电话 05-2720411#33134
电子邮件 tjlin@cs.ccu.edu.tw
研究专长 计算机结构、嵌入式系统、VLSI SOC设计
论文名称 期刊名称 全部作者 年度
ULV-turbo cache for an instantaneous performance boost on asymmetric architectures IEEE Trans. on VLSI Systems Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang and Tien-Fu Chen 2017
Speculative lookahead for energy-efficient microprocessors IEEE Transactions on Very Large Scale Integration (VLSI) Systems T. J. Lin and T. Y. Shyu 2016
Zero-counting and adaptive-latency cache using a voltage-guardband breakthrough for energy-efficient operations IEEE Transactions on Circuits and Systems – II: Express Briefs P. H. Wang, W. C. Cheng, Y. H. Yu, T. C. Kao, C. L. Tsai, P. Y. Chang, T. J. Lin, J. S. Wang, and T. F. Chen 2016
Cross-matching caches: dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors Integration, the VLSI Journal P. H. Wang, S. J. Tsai, R. Tanjung, T. J. Lin, J. S. Wang, and T. F. Chen 2016
System-level performance and power optimization for MPSoC - A memory access-aware approach ACM Transactions on Embedded Computing Ye-Jyun Lin, Chia-Lin Yang, Jiao-We Huang, Tay-Jyi Lin, Chih-Wen Hsueh, and Naehyuck Chang 2015
A 4R/2W register file design for UDVS microprocessors in 65nm CMOS IEEE Transactions on Circuits and Systems – II: Express Briefs P. Y. Chang, T. J. Lin, J. S. Wang, and Y. H. Yu 2012
Hierarchical circuit-switched NoC for multicore video processing Microprocessors and Microsystems Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin 2011
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters EURASIP Journal on Advances in Signal Processing Yu-Ting Kuo, Tay-Jyi Lin and Chih-Wei Liu 2011
Parallel architecture core (PAC) – the first multicore application processor SoC in Taiwan: Part I hardware architecture & software development tools Journal of Signal Processing Systems C. W. Chang, T. J. Lin, C. J. Wu, J. K. Lee, Y. H. Chu, and A. Y. Wu 2011
Design & implementation of low-power ANSI S1.11 filter bank for digital hearing aids IEEE Transactions on Circuits and Systems – I: Regular Papers Y. T. Kuo, T. J. Lin, Y. T. Li, and C. W. Liu 2010
年度 会议名称 论文名称 全部作者
2018 SOCC Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Ji Lin and Jinn-Shyan Wang
2018 ICSICT A low-power high-resolution all-digital on-chip jitter sensor for A 1-3 GHz clock generator Pei-Yuan Chou, Wei-Ling Lin, Chiang Hu Cheng, Tay-Jyi Lin, Jyh-Herng Wang and Jinn-Shyan Wang
2017 ASICON An all-N-type dynamic adder for ultra-low-leakage IoT devices Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin and Jinn-Shyan Wang
2016 VMC Timing margin prediction for energy-efficient and variation-resilient adaptive voltage scaling in microprocessor designs C. C. Huang, H. Yang, T. Y. Shyu, and T. J. Lin
2016 ICSIC A low-power low-cost built-in jitter measurement circuit for DDR4-2133 P. Y. Chou, W. L. Lin, T. J. Lin, J. H. Wang, J. S. Wang
2016 GCCE A low-complexity edge-preserved image compression algorithm for LCD overdrive C. Y. Chang, C. H. Huang, H. F. Chen, C. Yeh, Y. S. Chu, and T. J. Lin
2016 SOCC Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation Y. H. Ting, C. Y. Wang, Y. S. Chang, T. J. Lin, S. C. Chang, and J. S. Wang
2016 SOCC Variable-length VLIW encoding for code size reduction in embedded processors T. Y. Shyu, B. Y. Su, T. J. Lin, C. Yeh, T. F. Chen, and J. S. Wang,
2016 NANO Design of ultra-low-leakage near-threshold dynamic circuits in nano CMOS for IoT applications B. H. Chen, P. Y. Chou, Y. B. Fang, L. K. Yong, T. J. Lin, and J. S. Wang
2015 VMC Characterization of delay variations in modern FPGAs C. H. Kao, Z. H. Yang, C. L. Huang, Y. S. Chang, C. W. Wu, T. Y. Shyu, P. Y. Chou, T. J. Lin, and J. S. Wang
2015 ASICON Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches P. Y. Chou, I. C. Wu, J. W. Lin, X. Y. Lin, T. F. Chen, T. J. Lin, and J. S. Wang
2014 ICSICT Operation-condition and timing-error collaborative monitoring for fixed-latency AVS designs P. Y. Chou, C. L. Liou, J. S. Wang, and T. J. Lin
2014 Hot Chips Low-power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET) C. H. Huang, W. J. Chen, K. J. Chang, Y. H. Ting, K. C. Hsu, Y. F. Pan, C. C. Chen, Y. H. Chu, T. J. Lin, and J. S. Wang
2014 ICCE-TW Maintaining color fidelity for dual-shot HDR imaging C. Yeh, C. Y. Tsai, T. J. Lin, and J. I. Guo
2014 FTFC Adaptive variable-latency cache management for low-voltage caches Y. H. Yu, P. H. Wang, T. F. Chen, T. J. Lin, and J. S. Wang
2014 ICISA Accelerometer-based breathing signal acquisition with empirical mode decomposition B. Y. Yang, C. C. Chang, Y. H. Ting, J. W. Liao, H. L. Lin, T. J. Lin, C. Yeh, and J. S. Wang
2013 VLSI-SoC Variation-aware and adaptive-latency accesses for reliable low voltage caches P. H. Wang, W. C. Cheng, Y. H. Yu, T. C. Kao, C. L. Tsai, P. Y. Chang, T. J. Lin, J. S. Wang, and T. F. Chen
2013 VLSIC A 0.36V, 33.3μW 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS J. S. Wang, K. J. Chang, T. J. Lin, R. Wu, and C. Yeh
2013 ISSCC A 0.48V 0.57nJ/pixel video recording SoC in 65nm CMOS T. J. Lin, C. A. Chien, P. Y. Chang, C. W. Chen, P. H. Wang, T. Y. Shyu, C. Y. Chou, S. C. Luo, J. I. Guo, T. F. Chen, C. H. Chuang, Y. H. Chu, L. C. Cheng, H. M. Su, C. Jou, M. Ieong, C. W. Wu, and J. S. Wang
2012 ISCAS A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor S. H. Ou, C. W. Yeh, T. J. Lin, and C. W. Liu
2012 ASP-DAC Energy-efficient RISC design with on-demand circuit-level timing speculation T. J. Lin, Y. T. Kuo, Y. J. Tsai, T. Y. Shyu, and Y. H. Chu
2012 ASP-DA Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications S. C. Chen, C. C. Chen, W. C. Guo, T. J. Lin, and C. W. Yeh
2010 ICCAD Hierarchical memory scheduling for multimedia MPSoCs Y. J. Lin, C. L. Yang, T. J. Lin, J. W. Huang, and N. Chang
年度 计画名称 参与人 补助/委讬或合作机构
2018 低功耗智慧音讯计算平台 林泰吉 华邦电子股份有限公司
2018 基于铣削音讯之刀具寿命估算可行性评估报告 林泰吉 泰山电子股份有限公司
2018 构音异常沟通辅具之人工智能系统与芯片-子计画三：声学感知人工智能计算引擎 林泰吉 科技部
2017 低功耗微控制器 林泰吉 华邦电子股份有限公司
专利编号 专利名称 专利国别 着作人
US 9,064,153 Video device for realtime pedaling frequency estimation USA Tay-Jyi Lin, Ching-Wei Yeh, Yuan-Hsiang Miao, Shau-Chian TANG
US 8,589,718 Performance scaling device, processor having the same, and performance scaling method thereof USA Chi-Hung Lin, Pi-Cheng HSIAO, Tay-Jyi Lin, Gin-Kou Ma
US 8,499,188 Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal USA Chou-Kun LIN, Tay-Jyi Lin, Pi-Cheng HSIAO, Yuan-Hua Chu
US 8,972,699 Multicore interface with dynamic task management capability and task loading/offloading method thereof USA Tai-Ji Lin, Tien-Wei Hsieh, Yuan-Hua Chu, Shih-Hao Ou, Xiang-Sheng Deng, Chih-Wei Liu
US 7,877,741 Method and corresponding apparatus for compiling high-level languages into specific processor architectures USA Tay-Jyi Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen, I-Tao Liao, Po-Han Huang
奖项名称
2015年国立中正大学-青年学者奖
2014年全国大学校院智慧电子系统设计竞赛-佳作
2014年国家芯片系统设计中心-芯片制作优等设计奖
2013年旺宏金矽奖-优胜奖
2012年晶心科技-杰出系统芯片设计开发奖
2012年ARM Design Contest-季军