林 柏宏（國立中正大學電機工程學系）
職稱 教授
姓名 林 柏宏（國立中正大學電機工程學系）
聯絡電話 05-2720411#33204
電子郵件 marklin@ccu.edu.tw
研究專長 電子設計自動化、積體電路設計
論文名稱 期刊名稱 全部作者 年度
Clock-tree aware multi-bit flip-flop generation during placement for power optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) M. P.-H. Lin*, C.-C. Hsu, and Y.-C. Chen 2015
A novel analog physical synthesis methodology integrating existent design expertise IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) P.-H. Wu, M. P.-H. Lin*, T.-C. Chen, C.-F. Yeh, X. Li, and T.-Y. Ho 2015
Crosstalk-aware multi-bit flip-flop generation for power optimization Integration, the VLSI Journal C.-C. Hsu, M. P.-H. Lin*, and Y.-T. Chang 2015
Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) P.-H. Wu, M. P.-H. Lin*, T.-C. Chen, C.-F. Yeh, T.-Y. Ho, and B.-D. Liu 2014
Common-centroid capacitor layout generation considering device matching and parasitic minimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) M. P.-H. Lin*, Y.-T. He, V. W.-H. Hsiao, R.-G. Chang, and S.-Y. Lee 2013
1-D cell generation with printability enhancement IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) P.-H. Wu, M. P.-H. Lin*, T.-C. Chen, T.-Y. Ho, Y.-C. Chen, S.-R. Siao, and S.-H. Lin, 2013
Thermal-driven analog placement considering device matching IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) M. P.-H. Lin, H. Zhong, M. D. F. Wong, and Y.-W. Chang 2011
Post-Placement Power Optimization With Multi-Bit Flip-Flops IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Mark Po-Hung Lin; Chih-Cheng Hsu; Yao-Tsung Chang 2011
Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist Microelectronics Journal Shuenn-Yuh Lee, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, Mark Po-Hung Lin 2011
年度 會議名稱 論文名稱 全部作者
2014 Design Automation Conference (DAC-2014) Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC M. P.-H. Lin*, V. W.-H. Hsiao, and C.-Y. Lin
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Post-placement power optimization with multi-bit flip-flops Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsai, and S.-F. Chen
書名 全部作者 出版社
Analog Layout Synthesis: A Survey of Topological Approaches Hazem Abbas, Florin Balasa, Rafael Castro-Lopez, Yao-Wen Chang, Mohamed Dessouky, Gunhan Dundar, Michael Eick, Reem El-Adawi, Francisco V. Fernandez, Jan Freuer, Helmut Graeb, Goran Jerke, Jens Lienig, Mark Po-Hung Lin, Elisenda Roca, Hazem Said, Ulf Schlichtmann, Hussein Shahein, Martin Strasser, and Ahmet Unutulmaz Springer
年度 計畫名稱 參與人 補助/委託或合作機構
2018 Analog Circuit Structure Identification 林柏宏 安仲科技股份有限公司
2017 Parasitic-aware Capacitor Placement and Routing 林柏宏 安仲科技股份有限公司
2010 IBIS Collaboration 林柏宏 奇景科技產學合作計畫