Ching-Wei Yeh
Job Title Professor
Name Ching-Wei Yeh
Office Tel No. 05-2720411#33209
Email ieecwy@ccu.edu.tw
Research Expertise VLSI CAD、VLSI Design,、Testing and Fault Tolerance
Paper Title Journal Title Authors Year
Towards Process Variation-Aware Power Gating IEEE Transactions on Very Large Scale Integration (VLSI) Systems Ching-wei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang 2012
Design of high-performance CMOS level converters considering PVT variations IEICE Trans. Electronics Jinn-Shyan Wang*, Yu-Juey Chang, and Chingwei Yeh 2011
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays IEICE Transactions on Electronics Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH 2010
Year Conference Name Paper Title Authors
2016 GCCE A low-complexity edge-preserved image compression algorithm for LCD overdrive C. Y. Chang, C. H. Huang, H. F. Chen, C. Yeh, Y. S. Chu, and T. J. Lin
2013 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS Jian-Shiun Chen; Chingwei Yeh; Jinn-Shyan Wang
2013 VLSIC A 0.36V, 33.3μW 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS J. S. Wang, K. J. Chang, T. J. Lin, R. Wu, and C. Yeh
2012 ISCAS A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor S. H. Ou, C. W. Yeh, T. J. Lin, and C. W. Liu
2012 ASP-DA Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications S. C. Chen, C. C. Chen, W. C. Guo, T. J. Lin, and C. W. Yeh
Year Project Title Participator Unit
2019 科學工業園區研發精進產學合作計畫－人工智慧計算之高能效及抗變異設計平台 新竹科學工業園區管理局
2018 構音異常溝通輔具之人工智慧系統與晶片-子計畫二：構音異常語音澄析及時變特徵之技術探索 科技部
2018 科學工業園區研發精進產學合作計畫－抗變異設計技術與應用 新竹科學工業園區管理局
2017 聲音情境分析、應用及其節能電路系統設計-總計畫暨子計畫二：適用於聲音情境分析之低功率高效能EMD演算及架構設計 科技部
2017 先進CMOS的系統晶片可適性設計技術(III) 新竹科學工業園區管理局
2016 科學工業園區研發精進產學合作計畫－先進CMOS的系統晶片可適性設計技術(II) 新竹科學工業園區管理局
2015 視覺感測處理之具照度適應與能量調適的演算機制設計與硬體映射 葉經緯 科技部
2010 低功率ECG訊號擷取無線傳輸與接收晶片系統 葉經緯 國科會
2010 高速綠能CPU奈米晶片設計關鍵技術 葉經緯 智原科技
2009 低電壓及抗變異設計之關鍵技術 葉經緯 國科會微電子整合型計畫
Patent Number Patent Title Patent Country Authors
US7,865,025B2 DATA PROCESSING METHOD IN EMBEDDED BLOCK CODING WITH OPTIMIZED TRUNCATION MODULE USA Ying-Jie Xu, Ching-Wei Yeh, Jinn-Shyan Wang
Award Name Award Date
Dr. Ching-Wei Yeh directed a integration research project of National Science Council ” Apply for super low power SoC processor design technology” , and which won the “Excellent Project Award” of NSOC. 2007/10/17