Year | 2016 |
---|---|
Authors | P. H. Wang, S. J. Tsai, R. Tanjung, T. J. Lin, J. S. Wang, and T. F. Chen |
Paper Title | Cross-matching caches: dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors |
Journal Title | Integration, the VLSI Journal |
Vol.No | 54 |
Language | English |